In digital electronic systems, information is represented in binary format (1's and 0's). When binary information is passed from one point to another, there is always some chance that a mistake can be made; a 1 interpreted as a 0 or a 0 taken to be a 1. This can be caused by media defects, component failures, electronic noise, poor connections, deterioration due to age, and other factors. When a bit is mistakenly interpreted, a bit error has occurred.
In the field of integrated circuit semiconductor memory devices, redundancy is used primarily for fixing bit-line and word-line failures (i.e., for correcting "hard errors") in the devices to improve the production yield. If however redundancy is used, then the entire memory array may be increased.
A method of having essentially the same yield improvement while occupying less. area on a memory chip is to use an ECC technique. Error correction is useful in memory systems not only to correct "soft errors" due to noise or alpha particle hits, but also for the hard error correction. Error correction involves two steps. One is detecting the error and the other is correcting it. With such an error correction, it is possible to improve the reliability of the memory devices as well as yield.
More specifically, Hamming codes, which were first developed by Hamming in 1950, are frequently used for this purpose. With a Hamming code, error correction can be performed on many different bit field sizes. This entails using additional parity bits in the array. To determine the number of parity bits needed to correct a given number of data bits such as 8, 16, 32, 64, 128 bits, the following inequality must be satisfied EQU 2.sup.k.gtoreq.m+k+1 (1)
where `m` is the number of data bits to be corrected and `k` is the number of parity bits needed for correction. For example, if the number (m) of data bits is 8, the number (k) of parity bits is 4, and if the number (m) of data bits is 64, the number (k) of parity bits is 7.
There is a trade-off in that small bit fields allow fast error detection but require a large number of extra parity bits in the memory matrix. Large bit fields permit use of a smaller amount of extra matrix for the parity cells but error detection is slower.
Another type of error correction code which has been used on memories is the `horizontal-vertical (H-V)` error correction technique was developed by Edwards in 1981 and proposed for DRAMs by Burroughs. This method is also called bidirectional error correction.
In this method the memory is divided into blocks of a fixed size. To each byte, a horizontal parity bit is added. A vertical parity also generated and stored. During normal operation only the horizontal parity is checked which improves the time delay due to the error correction. If an error is detected when the horizontal parity bit is checked then the vertical parity bit is checked. The error is then found at the intersection of the two parities.
With above-described single error correction, a data word (e.g., 8, 16, 32, 64, 128 bits, etc.) with one bad bit can be corrected to recover the original information, whereas two bad bits can be detected, but not corrected.
Contemporary ECC techniques are disclosed, for example, in U.S. Pat. No. 4,903,268 for Semiconductor Memory Device Having On-Chip Error Check And Correction Functions issued to Hidaka et al., U.S. Pat. No. 4,958,352 for Semiconductor Memory Device With Error Check And Correcting Function issued to Noguchi et al., U.S. Pat. No. 5,313,425 for Semiconductor Memory Device Having An Improved Error Correction Capability issued to Lee et al., U.S. Pat. No. 5,448,578 for Electrically Erasable And Programmable Read Only Memory With An Error Check And Correction Circuit issued to Kim, and U.S. Pat. No. 5,765,185 for EEPROM Array With Flash-Like Core Having ECC Or A Write Cache Or Interruptible Load Cycles issued to Lambrache et al., all of whose disclosures are incorporated herein by reference.
Meanwhile, as semiconductor memory devices continue to increase in density and grow in area, neither redundancy nor error correction alone may be sufficient to give acceptable yield. Therefore, it is desirable to use the two methods effectively in combination to give improvement in long term in-system yield.
Desires toward efficient integration density for more expanded memory capacity have led to the development of multi-bit (or multi-level, or multi-state) technology by which a plurality of data bits are stored in one memory cell. Examples of contemporary multi-bit memory devices are disclosed in U.S. Pat. No. 5,262,984 for Non-Volatile Memory Device Capable Of Storing Multi-State Data issued to Noguchi et al, U.S. Pat. No. 5,457,650 for Apparatus And Method For Reading Multi-Level Data Stored In A Semiconductor Memory issued to Sugiura et al., U.S. Pat. No. 5,541,886 for Method And Apparatus For Storing Control Information In Multi-Bit Non-Volatile Memory Arrays issued to Hasbun, U.S. Pat. No. 5,740,104 for Multi-State Flash Memory Cell And Method For Programming Single Electron Differences issued to Forbes, U.S. Pat. No. 5,768,188 for Multi-State Non-Volatile Semiconductor Memory And Method For Driving The Same issued to Park et al., and U.S. Pat. No. 5,768,191 for Methods Of Programming Multi-State Integrated Circuit Memory Devices issued to Choi et al., whose disclosures are herein incorporated by reference.
In such ROM devices, a memory cell can be programmed to have one of four (4) data states of two bits, i.e., "11", "10", "01" and "00". Thus, a ROM cell can be programmed to be a two-bit device instead of just a one-bit device which advantageously doubles the amount of information that a memory device may contain, and so contributes to reduction of the cost per bit.
Considering small margin between threshold voltages corresponding to data states of low-voltage, high-density multi-bit memory devices, the adoption of ECC against bit fail is essential in improving the reliability of the memory devices as well as yield.
In general, there is a higher possibility that both of the two bits stored in such a multibit memory cell are susceptible to the soft and hard errors. If there occur two bit errors on a multibit cell, for example, when data "00" has changed into "11", or vice versa, then it is impossible to correct them using the conventional ECC techniques since only one bit error in a predetermined data word (e.g., 32, 64, or 128 bits) can be corrected by the techniques, so the accuracy of the error correction will be guaranteed.